Computer systems typically employ one or more interconnects to facilitate communication between system components, such as between processors and memory. Interconnects and/or expansion interfaces may also be used to support built-in and add on devices, such as IO (input/output) devices and expansion cards and the like. For many years after the personal computer was introduced, the primary form of interconnect was a parallel bus. Parallel bus structures were used for both internal data transfers and expansion buses, such as ISA (Industry Standard Architecture), MCA (Micro Channel Architecture), EISA (Extended Industry Standard Architecture) and VESA Local Bus. In the early 1990's Intel Corporation introduced the PCI (Peripheral Component Interconnect) computer bus. PCI improved on earlier bus technologies by not only increasing the bus speed, but also introducing automatic configuration and transaction-based data transfers using shared address and data lines.
As time progressed, computer processor clock rates were increasing at a faster pace than parallel bus clock rates. As a result, computer workloads were often limited by interconnect bottlenecks rather than processor speed. Although parallel buses support the transfer of a large amount of data (e.g., 32 or even 64 bits under PCI-X) with each cycle, their clock rates are limited by timing skew considerations, leading to a practical limit to maximum bus speed. To overcome this problem, high-speed serial interconnects were developed. Examples of early serial interconnects include Serial ATA, USB (Universal Serial Bus), FireWire, and RapidIO. Another standard serial interconnect that is widely used is PCI Express (PCIe), which was introduced in 2004 under the PCIe 1.0 standard.
More recently, architectures commonly referred to as “System on a Chip” (SoC), have become prevalent in the computer industry. Rather than have external interconnects between discreet components, SoC employ internal interconnect that facilitate communication between various embedded components, such as processor cores and other IP (Intellectual Property) blocks. These IP blocks are typically connected via one or more interconnect architectures, such as an interconnect mesh (e.g., a cross-bar type interconnect), also referred to as an interconnect fabric, or simply “fabric,” and associated with agents that manage communication between the IP core components using an applicable communication protocol implemented by the interconnect.
Designing the communication fabric for SoCs can be very challenging. As the number of IP blocks on SoCs continue to increase, the amount of traffic congestion on interconnect fabrics likewise increases. However, bus-based or hierarchical-tree based fabrics encounter severe wire congestion and timing closure issues as more IP blocks and associated agents are integrated onto an SoC, limiting the scalability of these interconnect architectures. As a result, the on-chip communication fabrics of SoCs are now moving from buses and hierarchical tree fabric structures to more sophisticated interconnect fabrics, such as Networks-on-Chip (NoC), hybrid architectures and so on due to their scalability, modularity and ease for design reuse.